Logic Verification Engineers

Job Requirement:
- BS/MS in Telecommunication/Electric-Electronics/IT/Software
- Experience: 0+ years in chip design
- Familiar with design and verification tools (Cadence/Mentor Graphic)
- Familiar with Linux/Unix working environment.
- Familiar with Universal Verification Methodology (UVM).
- Expertise in Verilog, System Verilog.
- Good problem solving & communication skills.
- Good ability to read & understand telecommunication standards/ books or write reports in English.
Preferred:
- Telecommunication knowledge: Ethernet, MPLS, TCP/IP, etc.
- Familiar with script languages: Python, Perl, C-Shell, Bash-Shell, TCL, etc.
**Working conditions:
- To work at E.town Building, PCs with strong configuration, modern lab (telecoms equipments and embedded systems in MAN/WAN networks, etc...)
- Offered competitive salary rate
- Dinner & parking allowance at e.town since probation time
- Other allowances: transportation, lunch, health insurance at international hospitals located in Viet Nam (such as Phap Viet, Colombia, An Sinh,..)
**Interested candidates please send the resume (describing education, experiences, and expected salary) with subject is the position you would like to apply Logic Verification Engineer via email or directly to the company address: Arrive Technologies Viet Nam, 10th Fl, e.town Building (1), 364 Cong Hoa, Tan Binh Dist., HCM City before Aug 30, 2018 (this deadline may be shortened if we get enough CV).