6 năm trước

Senior Analog Layout Design Engineer

Trên 30 triệu

Hồ Chí Minh

esilicon vietnam

Ngành nghề: IT Phần cứng - mạng Điện - Điện tử

Mức lương: Trên 30 triệu

Cập nhật: 05/09/2018 ( 6 năm trước)

6 năm trước

esilicon vietnam

IT Phần cứng - mạng Điện - Điện tử /

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29/09/2018 ( Đã quá hạn)

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Hồ Chí Minh

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MÔ TẢ CÔNG VIỆC

f You are a seasoned layout engineer who wants to become an expert of High–end Analog Mixed Signal Layouts. With latest process technologies and a great team player, this can be a perfect position for you.
Responsibilities
• Work on Custom Layout Analog IPs Like High Speed IOs, PLL, dLL, bandgap, high Speed Macros for HBMPHY/DDRPHY/Serdes, clock Trees...
• Floor Planning, Power Design, signal Routing Strategy, EMIR Awareness, Parasitic Optimization for Layout Blocks from Schematics
• Understand and apply Analog Layout techniques to ensure design meet performance with minimum area and good yield.
• Participate in building and enhancing layout flow for faster, higher quality design process.
• Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
• Complete all design quality checks and data quality checks.
• Work with Place and Route Engineer to integrate analog layouts into top level.
• Do design reviews across global team.
• May collaborate in package design (interposer design, rDL design).
• Work closely with design team in Viet Nam, USA and Italy to ensure the success of the whole product.
• May join research programs to implement new ideas for future products and flows.
• May lead a layout team to complete a full project.
• May mentor junior layout engineers or interns.

YÊU CẦU

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Bằng cấp

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Giới tính

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Độ tuổi

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+ Holding BS Degree in Electronics, Engineering, mechatronics, telecommunications.
. + Having 4 + years of experience in custom layout.
• Holding BS Degree in Electronics, Engineering, Electromechanics, telecommunications.
• 4 + years of experience in custom layout.
• Familiar with Layout Entry Tools: Cadence, synopsys.
• Familiar with Layout Verification Tools: Mentor Calibre, synopsys ICV.
• Understand Basic Semiconductor Fabrication Processes.
• Understand MOSFET Fundamentals.
• Understand Layout Techniques for High Speed, matching, ESD, latchup, antenna, EMIR.
• Experienced With Writing Layout Review Presentations and Layout Verification Reports.
• Locate in Ho Chi Minh City.
• Good English Communication.
• Good Team Player.
• Self Motivated
Opportunities
• Work with highly experienced global team and talented highly motivated Viet Nam engineering team.
• Work in a professional, innovative and fun environment.
• Working on most competitive designs such as: High Band Width Memory (HBM), PHY, high Speed PAM4, 56G/128G Serdes, as well as other designs in a large portfolio of Analog IP such as: High Speed LVDS IO Library, multiple Voltage Domain, gPIO, dDR IO Library, ONFI/SD IO Library, PLL, dLL, bandgap Reference, Power Management...
• Opportunity to get in touch with the complete flow of a real complicated Analog Mixed Signal Design: From Specification - RTL/Synthesis - Analog Circuit/Layout – Place & Route – Timing & Physical Sign Off - Packaging – Signal/Power Integrity – Silicon Bring Up.
• Chance to work with the latest possible technology nodes (16nm/14nm/10nm/7nm/5nm) from all foundries.
. • Clear career path of self - development to either Technical Expert or Design Leader/Manager
• Travel to USA, Europe and Asia for training or on site support.