Senior Analog Layout Engineer (Da Nang)

Summary
• eSilicon has revolutionized the chip business by partnering with tier-one suppliers to streamline the IC design and manufacturing processes, bringing our customers chips to market faster. eSilicon has a world-class custom IP team with a successful track record of first-time silicon success and demonstrated ability to provide niche IP and design services at leading-edge process nodes.
• Our Analog Mixed Signal IP Team is seeking for Senior Analog Layout Engineer to join our talented team.
• If you are a seasoned layout engineer who wants to become an expert of high-end Analog Mixed Signal layouts with latest process technologies and a great team player, this can be a perfect position for you.
Opportunities
• Work with highly experienced global team and talented highly motivated Viet Nam engineering team
• Work in a professional, innovative and fun environment.
• Working on most competitive designs such as: High Band Width Memory (HBM) PHY, High Speed PAM4 56G/128G Serdes as well as other designs in a large portfolio of Analog IP such as: High Speed LVDS IO library, Multiple Voltage Domain GPIO, DDR IO Library, ONFI/SD IO library, PLL, DLL, Bandgap Reference, Power Management ...
• Opportunity to get in touch with the complete flow of a real complicated Analog Mixed Signal Design: From Specification - RTL/Synthesis - Analog Circuit/Layout – Place & Route – Timing & Physical Sign Off - Packaging – Signal/Power Integrity – Silicon Bring Up.
• Chance to work with the latest possible technology nodes (16nm/14nm/10nm/7nm/5nm) from all foundries.
• Clear career path of self-development to either Technical Expert or Design Leader/Manager
• Travel to USA, Europe and Asia for training or on site support.
Benefits
• Competitive salary
• Very good insurance program for engineer and family members
• Strong internal training programs of softskills
• Participate in valuable conferences to learn and share knowledge with IC design community
Responsibilities
• Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for HBMPHY/DDRPHY/Serdes, Clock trees...
• Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
• Understand and apply Analog Layout techniques to ensure design meet performance with minimum area and good yield.
• Participate in building and enhancing layout flow for faster, higher quality design process.
• Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
• Complete all design quality checks and data quality checks
• Work with Place and Route engineer to integrate analog layouts into top level.
• Do design reviews across global team
• May collaborate in package design (interposer design, RDL design)
• Work closely with design team in Viet Nam, USA and Italy to ensure the success of the whole product.
• May join research programs to implement new ideas for future products and flows
• May lead a layout team to complete a full project
• May mentor junior layout engineers or interns

- Competitive salary - Very good insurance program for engineer and family members - Participate in valuable conferences to learn and share knowledge with IN DESIGN COMMUNITY