Design For Test (DFT) Engineer

- Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools.
- Knowledge about industrial standards and practices in DFT, including ATPG, JTAG and trade- offs between test quality and test time.
- Experience in Linus environment and writing/using scripting languages such as Perl, Tcl, etc
- Good written and oral communication skills in English.
- 2+ years of DFT experience: debugging ATPG and simulations. Newly graduated candidate with 7+ GPA is also welcome.
- Experience in Synthesis and STA is a plus.
** Benefits
- Private Healthcare Insurance for Employee and Family
- Lunch allowance, free drinks and snacks
- Competitive compensation and benefit package based on experience and competence
- Attractive performance bonus
All interested candidates are invited to send CV, motivation letter in English and the latest transcript to our HR department or via Vietnamworks.